Both programmable read-only-memories (PROMs) and programmable logic devices often use floating gate structures for storing data or establishing a desired logic function. One way to utilize floating gates, is to place the floating gate between a transistor channel and a control gate. The presence or absence of charge stored in the floating gate is used to alter the threshold of the transistor. For many non-volatile memories a cell is programmed by placing electrons on a floating gate and erased by removing electrons from the floating gate.
In conventional electrically programmable read-only-memories (EPROMs), electrons are placed on the floating gate by channel hot electron injection. In conventional electrically erasable read-only-memories (EEPROMs), Fowler-Nordheim tunnelling is used to charge and discharge the floating gate. In "Flash" EPROMs, floating gates are typically programmed by channel hot electron injection, and erased by Fowler-Nordheim tunnelling. Capacitive coupling, in these stacked gate structures, to the control gate, creates the field across the floating gate necessary to accumulate the electrons. One particularly compact structure utilizinhg a floating gate is the one transistor flash memory stacked cell, as set forth in U.S. Pat. No. 4,698,787 issued to Mukherjee et al. on Oct. 6, 1987 and entitled SINGLE TRANSISTOR ELECTRICALLY PROGRAMMABLE MEMORY DEVICE AND METHOD.
In order to maximize the capacitive coupling between the control gate and the floating gate, the dielectric separating the two is fabricated with as thin a layer as is possible, and from a material having a high dielectric constant. It is known in the prior art to pattern polysilicon to form the floating gate. The dielectric is then formed by creating an insulation film on the floating gate. This insulation film is typically created by thermally growing silicon oxide, depositing silicon nitride, and then re-oxidizing the silicon nitride to create an oxidized-nitride-oxide (ONO) layer. Because the control gate and the floating gate are typically patterned from polysilicon, this dielectric layer is often referred to as the inter-poly dielectric. Similarly, a thin dielectric layer referred to as tunnel oxide, exists between floating poly and the channel.
A problem that occurs during the fabrication of stacked gate structures is that unintentional charging of the conductive layers, such as the floating gate and the control gate, causes breakdown of the inter-poly dielectric during fabrication. Many of the integrated circuit fabrication steps, reactive ion etching (RIE) in particular, can cause charge accumulation in these conductive layers. For the case of stacked gate structures, the control gates can accumulate charge during these fabrication steps causing the inter-poly dielectric layer to breakdown thereby shorting the floating gate to the control gate. This destroys the memory cell. While the same problem may occur in the tunnel dielectric, between the floating gate and substrate, breakdown of the inter-poly dielectric is more likely because the breakdown voltage of the tunnel dielectric is greater than that of the inter-poly dielectric.
It is known in the prior art to modify MOS fabrication processes to prevent the breakdown of MOS gate dielectrics due to charge accumulation. Shibata et al. in U.S. Pat. No. 4,543,597 issued on Sep. 24, 1985 and entitled DYNAMIC SEMICONDUCTOR MEMORY AND MANUFACTURING METHOD THEREOF, and Seiichi Mori in U.S. Pat. No. 5,049,514 issued on Sep. 17, 1991 and entitled METHOD OF MAKING A MOS DEVICE HAVING A POLYCIDE GATE, both teach fabrication methods in which the gate oxide is protected by coupling a polysilicon gate to the substrate by way of a p-n junction. If the gate is charged with one type of polarity, the p-n junction is forward biased and the gate is discharged to the substrate. If the gate is charged to the opposite polarity, reverse bias leakage of the p-n junction discharges the gate. Alternatively, the gate makes ohmic contact with the substrate by way of a p-n junction during the first part of the fabrication process. In either method, the gate is then subsequently isolated from the substrate by an etch or oxidation step.
Junji Kiyono in U.S. Pat. No. 5,083,172 issued on Jan. 21, 1992 and entitled DYNAMIC RANDOM ACCESS MEMORY DEVICE FABRICATED WITH TWO KINDS OF FIELD EFFECT TRANSISTOR DIFFERENT IN THICKNESS OF GATE OXIDE FILMS discloses a dynamic random access memory wherein gate electrodes are coupled to a first gate oxide to form active devices, and to a second gate oxide, thinner than the first. In the event the gate electrodes accumulate undesirable charge, a discharge path is formed through the second gate oxide protecting the first gate oxide of the active devices.
None of the references discussed above teach a method of eliminating the adverse effects of charge accumulation in the fabrication of stacked gate structures. What is needed is a method of eliminating the adverse effects of charge accumulation in the fabrication of stacked gate structures. What is further needed is a method of fabricating a semiconductor device with a stacked gate structure and an inter-poly dielectric wherein charge damage to the inter-poly dielectric is minimized during fabrication.